 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LTC3720 Single Phase VRM8.5 Current Mode Step-Down Controller FEATURES s s s s s s s s s s s s s s s s s s s DESCRIPTIO 5-Bit Programmable Output Voltage: 1.05V to 1.825V (VRM8.5) No Sense Resistor Required 2% to 87% Duty Cycle at 200kHz tON(MIN) 100ns Supports Active Voltage Positioning True Current Mode Control Stable with Ceramic COUT Dual N-Channel MOSFET Synchronous Drive Power Good Output Voltage Monitor Wide VIN Range: 4V to 36V 1% 0.8V Reference Adjustable Current Limit Adjustable Switching Frequency Forced Continuous Control Pin Programmable Soft-Start Output Overvoltage Protection Optional Short-Circuit Shutdown Timer Micropower Shutdown: IQ < 30A Available in 28-Lead Narrow SSOP Package The LTC(R)3720 is a synchronous step-down switching regulator controller for CPU power. An output voltage between 1.05V and 1.825V is selected by a 5-bit code (Intel VRM8.5 VID specification). The controller uses a valley current control architecture to deliver very low duty cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in VIN and VOUT. Discontinuous mode operation provides high efficiency operation at light loads. A forced continuous control pin reduces noise and RF interference and can assist secondary winding regulation by disabling discontinuous mode operation when the main output is lightly loaded. Fault protection is provided by internal foldback current limiting, an output overvoltage comparator and optional short-circuit shutdown timer. Soft-start capability for supply sequencing is accomplished using an external timing capacitor. The regulator current limit level is also user programmable. Wide supply range allows operation from 4V to 36V at the input. , LTC and LT are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. APPLICATIO S s s Power Supplies for Pentium(R) Processors Notebook Computers and Servers TYPICAL APPLICATIO LTC3720 PGOOD ION 0.1F RUN/SS 470pF 20k SGND BOOST VCC INTVCC VID4 VID3 5-BIT VID VID2 VID1 VID0 SENSE + BG PGND SENSE VOSENSE ITH VIN TG SW 330k IRF7811W x2 0.33F CMDSH-3 L1 1H 10F x5 VIN 5V TO 24V + UPS840 + COUT 270F 2V x4 EFFICIENCY (%) VOUT 1.05V TO 1.825V 20A 4.7F IRF7811W x3 COUT: CORNELL DUBILIER ESRE271M02B L1: SUMIDA CEP125-IROMC 3720 F01a Figure 1. High Efficiency Step-Down Converter U Efficiency vs Output Current 100 VOUT = 1.45V 95 L1 = 1H 90 85 80 75 70 65 60 55 0.01 1 10 0.1 OUTPUT CURRENT (A) 100 3720 F01b U U VIN = 5V VIN = 15V 3720f 1 LTC3720 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW RUN/SS VON PGOOD VRNG FCB ITH SGND ION VFB 1 2 3 4 5 6 7 8 9 28 BOOST 27 TG 26 SW 25 SENSE + 24 SENSE - 23 PGND 22 BG 21 INTVCC 20 VIN 19 EXTVCC 18 VCC 17 VID4 16 VID3 15 VID2 Input Supply Voltage VIN, ION ..................................................36V to - 0.3V Boosted Topside Driver Supply Voltage BOOST .................................................. 42V to - 0.3V SW, SENSE + Voltages ................................. 36V to - 5V EXTVCC, (BOOST - SW), RUN/SS, VCC VID0-VID4, PGOOD Voltages ..................... 7V to - 0.3V FCB, VON, VRNG Voltages .......... INTVCC + 0.3V to - 0.3V ITH, VFB, VOSENSE Voltages ....................... 2.7V to - 0.3V TG, BG, INTVCC, EXTVCC Peak Currents .................... 2A TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA Operating Ambient Temperature Range LTC3720EGN (Note 2) ........................ - 40C to 85C Junction Temperature (Note 3) ............................ 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C ORDER PART NUMBER LTC3720EGN SGND 10 VFB 11 VOSENSE 12 VID0 13 VID1 14 GN PACKAGE 28-LEAD NARROW PLASTIC SSOP TJMAX = 125C, JA = 95C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL IQ PARAMETER Input DC Supply Current Normal Shutdown Supply Current Feedback Reference Voltage Feedback Voltage Line Regulation Feedback Voltage Load Regulation Feedback Pin Input Current Error Amplifier Transconductance Forced Continuous Threshold Forced Continuous Pin Current On-Time Minimum On-Time Minimum Off-Time Maximum Current Sense Threshold VSENSE- - VSENSE+ Minimum Current Sense Threshold VSENSE- - VSENSE+ Output Overvoltage Fault Threshold Output Undervoltage Fault Threshold RUN Pin Start Threshold Main Control Loop The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 15V unless otherwise noted. CONDITIONS MIN TYP MAX UNITS 900 15 ITH = 1.2V (Note 4) VIN = 4V to 30V, ITH = 1.2V (Note 4) ITH = 0.5V to 1.9V (Note 4) ITH = 1.2V (Note 4) q q q 2000 30 0.808 - 0.3 50 2 0.84 -2 300 575 100 400 153 107 214 VFB VFB(LINEREG) VFB(LOADREG) IFB gm(EA) VFCB IFCB tON tON(MIN) tOFF(MIN) VSENSE(MAX) 0.792 0.800 0.002 - 0.05 -5 1.4 0.76 200 425 1.7 0.8 -1 250 500 50 250 VFCB = 0.8V ION = 60A, VON = 1.5V ION = 30A, VON = 1.5V ION = 180A, VON = 0V ION = 60A, VON = 1.5V VRNG = 1V, VFB = 0.76V VRNG = 0V, VFB = 0.76V VRNG = INTVCC, VFB = 0.76V VRNG = 1V, VFB = 0.84V VRNG = 0V, VFB = 0.84V VRNG = INTVCC, VFB = 0.84V 5.5 520 q q q q 113 79 158 133 93 186 - 67 - 47 - 93 7.5 600 1.5 VSENSE(MIN) VFB(OV) VFB(UV) VRUN/SS(ON) 9.5 680 2 0.8 2 U A A V %/V % nA mS V A ns ns ns ns mV mV mV mV mV mV % mV V 3720f W U U WW W LTC3720 ELECTRICAL CHARACTERISTICS SYMBOL VRUN/SS(LE) VRUN/SS(LT) IRUN/SS(C) IRUN/SS(D) VIN (UVLO) TG RUP TG RDOWN BG RUP BG RDOWN TG tr TG tf BG tr BG tf VINTVCC VLDO(LOADREG) VEXTVCC VEXTVCC VEXTVCC(HYS) PGOOD Output VFBH VFBL VFB(HYS) VPGL VID DAC VCC VVID(T) VVID(LEAK) VOSENSE RPULLUP RVID IVCC Operating Supply Voltage Range VID0-VID4 Logic Threshold Voltage VID0-VID4 Leakage Current DAC Output Accuracy Pull-Up Resistance on VID Resistance from VOSENSE to VFB Supply Current PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysteresis PGOOD Low Voltage PARAMETER RUN Pin Latchoff Enable Threshold RUN Pin Latchoff Threshold Soft-Start Charge Current Soft-Start Discharge Current Undervoltage Lockout TG Driver Pull-Up On Resistance TG Driver Pull-Down On Resistance BG Driver Pull-Up On Resistance BG Driver Pull-Down On Resistance TG Rise Time TG Fall Time BG Rise Time BG Fall Time Internal VCC Voltage Internal VCC Load Regulation EXTVCC Switchover Voltage EXTVCC Switch Drop Voltage EXTVCC Switchover Hysteresis The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 15V unless otherwise noted. CONDITIONS RUN/SS Pin Rising RUN/SS Pin Falling - 0.5 0.8 VIN Falling VIN Rising TG High TG Low BG High BG Low CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF 6V < VIN < 30V, VEXTVCC = 4V ICC = 0mA to 20mA, VEXTVCC = 4V ICC = 20mA, VEXTVCC Rising ICC = 20mA, VEXTVCC = 5V q q q q MIN TYP 4 3.5 - 1.2 1.8 3.4 3.5 2 2 3 1 20 20 20 20 MAX 4.5 -3 3 3.9 4.0 3 3 4 2 UNITS V V A A V V ns ns ns ns Internal VCC Regulator 4.7 4.5 5 - 0.1 4.7 150 200 VFB Rising VFB Falling VFB Returning IPGOOD = 5mA 3.1 VCC = 3.3V VVID0-VVID4 = VCC VOSENSE Programmed from 1.05V to 1.825V (Note 5), VCC = 5V VDIODE = 0.6V (Note 6) (Note 7) - 0.25 28 6 0.4 1.2 0.01 0 40 10 1 5.5 - 5.5 7.5 - 7.5 1 0.15 9.5 - 9.5 2 0.4 5.5 2 1 0.25 56 14 10 300 5.3 2 V % V mV mV % % % V V V A % k k A Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3720E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3720EGN: TJ = TA + (PD * 95C/W) Note 4: The LTC3720 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH). Note 5: The LTC3720 VID DAC is tested in a feedback loop that adjusts VOSENSE to achieve a specified feedback voltage (VFB = 0.8V) for each DAC VID code. Note 6: Each built-in pull-up resistor attached to VID inputs also has a series diode connected to VCC to allow input voltages higher than the VCC supply without damage or clamping. (See Operation section for further details.) Note 7: Supply current is specified with all VID inputs floating. Due to the internal pull-ups on the VID pins, the supply current will increase depending on the number of grounded VID lines. Each grounded VID line will draw approximately (VCC - 0.6V)/40k mA. (See Operation section for further details.) 3720f 3 LTC3720 TYPICAL PERFOR A CE CHARACTERISTICS Current Sense Threshold vs ITH Voltage 300 VRNG = 2V 1.4V 1V ON-TIME (ns) 1k 10k CURRENT SENSE THRESHOLD (mV) 200 100 0.7V 0.5V ON-TIME (ns) 0 -100 10 -200 0 0.5 1.0 1.5 2.0 ITH VOLTAGE (V) On-Time vs Temperature 300 250 200 150 100 50 0 -50 -25 MAXIMUM CURRENT SENSE THRESHOLD (mV) IION = 30A VVON = 0V VRNG = 1V 125 100 75 50 25 0 0 0.2 0.4 VFB (V) 0.6 0.8 3720 G05 MAXIMUM CURRENT SENSE THRESHOLD (mV) ON-TIME (ns) 50 25 75 0 TEMPERATURE (C) Maximum Current Sense Threshold vs RUN/SS Voltage MAXIMUM CURRENT SENSE THRESHOLD (mV) VRNG = 1V MAXIMUM CURRENT SENSE THRESHOLD (mV) 150 125 100 75 50 25 0 140 FEEDBACK REFERENCE VOLTAGE (V) 1.5 2 2.5 3 RUN/SS VOLTAGE (V) 4 UW 2.5 3720 G01 On-Time vs ION Current VVON = 0V 1000 On-Time vs VON Voltage IION = 30A 800 600 400 100 200 3.0 1 10 ION CURRENT (A) 100 3720 G02 0 0 2 1 VON VOLTAGE (V) 3 3720 G02 Current Limit Foldback 150 300 250 200 150 100 50 0 Maximum Current Sense Threshold vs VRNG Voltage 100 125 0.5 0.75 1.0 1.25 1.5 VRNG VOLTAGE (V) 1.75 2.0 3720 G04 3720 G06 Maximum Current Sense Threshold vs Temperature 150 VRNG = 1V Feedback Reference Voltage vs Temperature 0.82 0.81 130 0.80 120 0.79 110 3.5 3729 G07 100 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 0.78 -50 -25 75 0 25 50 TEMPERATURE (C) 100 125 3720 G08 3720 G09 3720f LTC3720 TYPICAL PERFOR A CE CHARACTERISTICS Error Amplifier gm vs Temperature 2.0 1200 1000 EXTVCC OPEN 1.8 INPUT CURRENT (A) gm (mS) 1.6 INTVCC (%) 1.4 1.2 1.0 -50 -25 50 25 0 75 TEMPERATURE (C) EXTVCC Switch Resistance vs Temperature 10 0 -0.25 FCB PIN CURRENT (A) EXTVCC SWITCH RESISTANCE () 8 FCB PIN CURRENT (A) 6 4 2 0 -50 -25 50 25 0 75 TEMPERATURE (C) RUN/SS Latchoff Thresholds vs Temperature UNDERVOLTAGE LOCKOUT THRESHOLD (V) 5.0 4.0 RUN/SS THRESHOLD (V) 4.5 LATCHOFF ENABLE 4.0 3.5 LATCHOFF THRESHOLD 3.0 -50 -25 UW 100 3720 G10 Input and Shutdown Currents vs Input Voltage 60 50 0 INTVCC Load Regulation -0.1 SHUTDOWN CURRENT (A) 800 SHUTDOWN 600 400 200 EXTVCC = 5V 0 40 30 20 10 0 0 5 20 15 25 10 INPUT VOLTAGE (V) 30 35 -0.2 -0.3 -0.4 125 -0.5 0 10 30 40 20 INTVCC LOAD CURRENT (mA) 50 3720 G12 3720 G11 FCB Pin Current vs Temperature 3 RUN/SS Pin Current vs Temperature 2 PULL-DOWN CURRENT 1 -0.50 -0.75 -1.00 -1.25 -1.50 -50 -25 0 PULL-UP CURRENT -1 100 125 50 25 75 0 TEMPERATURE (C) 100 125 -2 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 3720 G13 3720 G14 3720 G15 Undervoltage Lockout Threshold vs Temperature 3.5 3.0 2.5 75 0 25 50 TEMPERATURE (C) 100 125 2.0 -50 -25 75 0 25 50 TEMPERATURE (C) 100 125 3720 G16 3720 G17 3720f 5 LTC3720 TYPICAL PERFOR A CE CHARACTERISTICS Transient Response (Forced Continuous Mode) VOUT 50mV/DIV VOUT 50mV/DIV IL 10A/DIV 20s/DIV LOAD STEP = 0A TO 15A VIN = 15V VOUT = 1.5V FCB = 0V FIGURE 7 CIRCUIT PI FU CTIO S RUN/SS (Pin 1): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/F) and the time delay for overcurrent latchoff (see Applications Information). Forcing this pin below 0.8V shuts down the device. VON (Pin 2): On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage makes the on-time proportional to VOUT. The comparator input defaults to 0.7V when the pin is grounded, 2.4V when the pin is tied to INTVCC. PGOOD (Pin 3): Power Good Output. Open drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regulation point. VRNG (Pin 4): Sense Voltage Range Input. The voltage at this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a resistive divider from INTVCC. The nominal sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to INTVCC. FCB (Pin 5): Forced Continuous Input. Tie this pin to ground to force continuous synchronous operation at low load or to INTVCC to enable discontinuous mode operation at low load. ITH (Pin 6): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.8V corresponding to zero sense voltage (zero current). SGND (Pin 7, 10): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. ION (Pin 8): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. VFB (Pin 9, 11): Error Amplifier Feedback Input. This pin connects to both the error amplifier input and to the output of the internal resistive divider. It can be used to attach additional compensation components if desired. VOSENSE (Pin 12): Output Voltage Sense. The output voltage connects here to the input of the internal resistive feedback divider. VID0-VID4 (Pins 13, 14, 15, 16, 17): VID Digital Inputs. The voltage identification (VID) code sets the internal feedback resistor divider ratio for different output voltages as shown in Table 1. If unconnected, the pins are pulled high by internal 40k pull-up resistors. 3720f 6 UW Transient Response (Discontinuous Mode) IL 10A/DIV 3720 G18 20s/DIV LOAD STEP = 1A TO 15A VIN = 15V VOUT = 1.5V FCB = INTVCC FIGURE 7 CIRCUIT 3720 G19 U U U LTC3720 PI FU CTIO S VCC (Pin 18): Power Supply Voltage for VID. Range is from 3.1V to 5.5V. EXTVCC (Pin 19): External VCC Input. When EXTVCC exceeds 4.7V, an internal switch connects this pin to INTVCC and shuts down the internal regulator so that controller and gate drive power is drawn from EXTVCC. Do not exceed 7V at this pin and ensure that EXTVCC < VIN. VIN (Pin 20): Main Input Supply. Decouple this pin to PGND with an RC filter (1, 0.1F). INTVCC (Pin 21): Internal 5V Regulator Output. The driver and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 4.7F low ESR tantalum capacitor. BG (Pin 22): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and INTVCC. PGND (Pin 23): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET, the (-) terminal of CVCC and the (-) terminal of CIN. SENSE- (Pin 24): Current Sense Comparator Input. The (-) input is normally connected to PGND. SENSE + (Pin 25): Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW node unless using a sense resistor (see Applications Information). SW (Pin 26): Switch Node. The (-) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below ground up to VIN. TG (Pin 27): Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. BOOST (Pin 28): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below INTVCC up to VIN + INTVCC. U U U 3720f 7 LTC3720 FU CTIO AL DIAGRA RON 2 VON 8 ION 0.7V 2.4V 1 OST F V tON = VON (10pF) IION R S Q FCNT ON + ICMP 20k + IREV SWITCH LOGIC - 1.4V - SHDN OV VRNG 4 PGND x 23 SENSE - 24 PGOOD 3 3.3A VOSENSE 12 1 240k Q2 Q4 Q6 ITHB 1V UV R2 10k 0.7V Q3 Q1 Q5 OV + - x4 0.8V SS EA RUN SHDN 0.6V 0.8V 6 ITH CC1 RUN/SS 1 CSS VFB 11 9 VFB RC 8 + - W VIN 5 FCB 4.7V 1A 19 EXTVCC 20 VIN - + U U + CIN + - 0.8V REF 0.8V 5V REG - + BOOST 28 TG 27 SW 26 SENSE + 25 INTVCC 21 BG 22 DB L1 CB M1 + CVCC M2 + COUT + - 0.74V x5 (ALL VID PINS) VCC 40k 13 VID0 + - 0.86V VID DAC 14 VID1 15 VID2 16 VID3 17 VID4 18 VCC R1 SGND 10 7 SGND 3711 FD 1.2A 6V + - 0.6V 3720f LTC3720 OPERATIO Main Control Loop The LTC3720 is a current mode controller for DC/DC step-down converters. In normal operation, the top MOSFET is turned on for a fixed interval determined by a one-shot timer OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between the SENSE - and SENSE + pins using either the bottom MOSFET on-resistance or a separate sense resistor. The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this voltage by comparing the feedback signal VFB from the output voltage with an internal 0.8V reference. The feedback voltage is derived from the output voltage by a resistive divider DAC that is set by the VID code pins VID0-VID4. If the load current increases, it causes a drop in the feedback voltage relative to the reference. The ITH voltage then rises until the average inductor current again matches the load current. At low load currents, the inductor current can drop to zero and become negative. This is detected by current reversal comparator IREV which then shuts off M2, resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.8V) to initiate another cycle. Discontinuous mode operation is disabled by comparator F when the FCB pin is brought below 0.8V, forcing continuous synchronous operation. The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in VIN and VOUT. The nominal frequency can be adjusted with an external resistor RON. U (Refer to Functional Diagram) Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a 7.5% window around the regulation point. Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on and held on until the overvoltage condition clears. Foldback current limiting is provided if the output is shorted to ground. As VFB drops, the buffered current threshold voltage ITHB is pulled down by clamp Q3 to a 1V level set by Q4 and Q6. This reduces the inductor valley current level to one sixth of its maximum value as VFB approaches 0V. Pulling the RUN/SS pin low forces the controller into its shutdown state, turning off both M1 and M2. Releasing the pin allows an internal 1.2A current source to charge up an external soft-start capacitor CSS. When this voltage reaches 1.5V, the controller turns on and begins switching, but with the ITH voltage clamped at approximately 0.6V below the RUN/SS voltage. As CSS continues to charge, the soft-start current limit is removed. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the internal controller circuitry is derived from the INTVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is recharged from INTVCC through an external Schottky diode DB when the top MOSFET is turned off. When the EXTVCC pin is grounded, an internal 5V low dropout regulator supplies the INTVCC power from VIN. If EXTVCC rises above 4.7V, the internal regulator is turned off, and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source connected to EXTVCC, such as an external 5V supply or a secondary output from the converter, to provide the INTVCC power. Voltages up to 7V can be applied to EXTVCC for additional gate drive. If the input voltage is low and INTVCC drops below 3.5V, undervoltage lockout circuitry prevents the power switches from turning on. 3720f 9 LTC3720 APPLICATIO S I FOR ATIO The basic LTC3720 application circuit is shown in Figure 1. External component selection is primarily determined by the maximum load current and begins with the selection of the sense resistance and power MOSFET switches. The LTC3720 can use either a sense resistor or the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specification. Maximum Sense Voltage and VRNG Pin Inductor current is determined by measuring the voltage across a sense resistance that appears between the SENSE - and SENSE + pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately (0.133)VRNG. The current mode control loop will not allow the inductor current valleys to exceed (0.133)VRNG/RSENSE. In practice, one should allow some margin for variations in the LTC3720 and external component values and a good guide for selecting the sense resistance is: VRNG RSENSE = 10 * IOUT (MAX) An external resistive divider from INTVCC can be used to set the voltage of the VRNG pin between 0.5V and 2V resulting in nominal sense voltages of 50mV to 200mV. Additionally, the VRNG pin can be tied to SGND or INTVCC in which case the nominal sense voltage defaults to 70mV or 140mV, respectively. The maximum allowed sense voltage is about 1.33 times this nominal value. Connecting the SENSE + and SENSE - Pins The LTC3720 can be used with or without a sense resistor. When using a sense resistor, it is placed between the source of the bottom MOSFET M2 and ground. Connect the SENSE + pin to the source of the bottom MOSFET and the SENSE - pin to PGND so that the resistor appears 10 U between the SENSE + and SENSE - pins. Kelvin connections at the sense resistor ensure accurate current sensing. Using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. Alternatively, one can eliminate the sense resistor and use the bottom MOSFET as the current sense element by simply connecting the SENSE + pin to the switch node SW at the drain of the bottom MOSFET and keep SENSE - connected to PGND. This improves efficiency, but one must carefully choose the MOSFET on-resistance as discussed below. Power MOSFET Selection The LTC3720 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage V(GS)TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The gate drive voltage is set by the 5V INTVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3720 applications. If the input voltage is expected to drop below 5V, then sub-logic level threshold MOSFETs should be considered. When the bottom MOSFET is used as the current sense element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: W UU RDS(ON)(MAX) = RSENSE T The T term is a normalization factor (unity at 25C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/C as shown in Figure 2. For a maximum temperature of 100C, using a value T = 1.3 is reasonable. The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and 3720f LTC3720 APPLICATIO S I FOR ATIO 2.0 T NORMALIZED ON-RESISTANCE 1.5 1.0 0.5 0 - 50 50 100 0 JUNCTION TEMPERATURE (C) 150 3720 F02 Figure 2. RDS(ON) vs. Temperature the load current. When the LTC3720 is operating in continuous mode, the duty cycles for the MOSFETs are: D TOP DBOT V = OUT VIN V -V = IN OUT VIN The resulting power dissipation in the MOSFETs at maximum output current are: PTOP = DTOP IOUT(MAX)2 T(TOP) RDS(ON)(MAX) + k VIN2 IOUT(MAX) CRSS f PBOT = DBOT IOUT(MAX)2 T(BOT) RDS(ON)(MAX) Both MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are largest at high input voltages. The constant k = 1.7A-1 can be used to estimate the amount of transition loss. The bottom MOSFET losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. Operating Frequency The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. U The operating frequency of LTC3720 applications is determined implicitly by the one-shot timer that controls the on-time tON of the top MOSFET switch. The on-time is set by the current into the ION pin and the voltage at the VON pin according to: tON = VVON (10pF ) IION W UU Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency operation as the input supply varies: f= VOUT VVON RON (10pF ) [Hz] To hold frequency constant during output voltage changes, tie the VON pin to VOUT. The VON pin has internal clamps that limit its input to the one-shot timer. If the pin is tied below 0.7V, the input to the one-shot is clamped at 0.7V. Similarly, if the pin is tied above 2.4V, the input is clamped at 2.4V. Because the voltage at the ION pin is about 0.7V, the current into this pin is not exactly inversely proportional to VIN, especially in applications with lower input voltages. To correct for this error, an additional resistor RON2 connected from the ION pin to the 5V INTVCC supply will further stabilize the frequency. RON2 = 5V RON 0.7V Changes in the load current magnitude will also cause frequency shift. Parasitic resistance in the MOSFET switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. By lengthening the on-time slightly as current increases, constant frequency operation can be maintained. This is accomplished with a resistive divider from the ITH pin to the VON pin and VOUT. The values required will depend on the parasitic resistances in the specific application. A good starting point is to feed about 25% of the voltage change at the ITH pin to the VON pin as 3720f 11 LTC3720 APPLICATIO S I FOR ATIO RVON1 30k VOUT RVON2 100k RC ITH CC 3720 F03a VON CVON 0.01F LTC3720 (3a) Figure 3. Correcting Frequency Shift with Load Current Changes shown in Figure 3a. Place capacitance on the VON pin to filter out the ITH variations at the switching frequency. The resistor load on ITH reduces the DC gain of the error amp and degrades load regulation, which can be avoided by using the PNP emitter follower of Figure 3b. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: V V IL = OUT 1 - OUT VIN fL Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: VOUT V L= 1 - OUT f IL(MAX) VIN(MAX) 12 U RVON1 3k VOUT 10k INTVCC Q1 2N5087 RVON2 10k CVON 0.01F RC ITH CC 3720 F03b W UU VON LTC3720 (3b) Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool M(R) cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. Schottky Diode D1 Selection The Schottky diode D1 shown in Figure 1 conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. CIN and COUT Selection The input capacitance CIN is required to filter the square wave current at the drain of the top MOSFET. Use a low ESR capacitor sized to handle the maximum RMS current. IRMS IOUT (MAX) VOUT VIN VIN -1 VOUT Kool M is a registered trademark of Magnetics, Inc. 3720f LTC3720 APPLICATIO S I FOR ATIO This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX) / 2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple VOUT is approximately bounded by: 1 VOUT IL ESR + 8fC OUT Since IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. To dampen input voltage transients, add a small 5F to 50F aluminum electrolytic capacitor with an ESR in the range of 0.5 to 2. High U performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from INTVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications a 0.1F to 0.47F X5R or X7R dielectric capacitor is adequate. Discontinuous Mode Operation and FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.8V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. The load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary with changes in VIN. Tying the FCB pin below the 0.8V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. In addition to providing a logic input to force continuous operation, the FCB pin provides a means to maintain a flyback winding output when the primary is operating in discontinuous mode. The secondary output VSEC is normally set as shown in Figure 4 by the turns ratio N of the transformer. However, if the controller goes into discontinuous mode and halts switching due to a light primary load current, then VSEC will droop. An external resistor divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN) below which continuous operation is forced until VSEC has risen above its minimum. R4 VSEC(MIN) = 0.8V 1 + R3 3720f W UU 13 LTC3720 APPLICATIO S I FOR ATIO + VIN OPTIONAL EXTVCC CONNECTION 5V < VSEC < 7V TG LTC3720 EXTVCC SW R4 FCB R3 SGND SENSE + BG PGND VIN CIN 1N4148 + T1 1:N *+ Figure 4. Secondary Output Loop and EXTVCC Connection Fault Conditions: Current Limit and Foldback The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3720, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSNS(MAX) 1 + IL RDS(ON) T* 2 The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. 14 U VSEC CSEC 1F VOUT COUT W * UU To further limit current in the event of a short circuit to ground, the LTC3720 includes foldback current limiting. If the output falls by more than 25%, then the maximum sense voltage is progressively lowered to about one sixth of its full value. Minimum Off-time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3720 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 350ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON 3720 F04 Output Voltage Programming The output voltage is digitally set to levels between 1.05V and 1.825V using the voltage identification (VID) inputs VID0-VID4. An internal 5-bit DAC configured as a precision resistive voltage divider sets the output voltage in increments according to Table 1. The VID codes are compatible with Intel VRM8.5 processor specifications. Each VID input is pulled up by an internal 40k pull-up resistor from the INTVCC supply and includes a series diode to prevent damage from VID inputs that exceed the supply. INTVCC Regulator An internal P-channel low dropout regulator produces the 5V supply that powers the drivers and internal circuitry within the LTC3720. The INTVCC pin can supply up to 50mA RMS and must be bypassed to ground with a minimum of 4.7F low ESR capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers. Applications using large MOSFETs with a high input voltage and high frequency of *Use RSENSE value if a sense resistor is connected between SENSE + and SENSE -. 3720f LTC3720 APPLICATIO S I FOR ATIO Table 1. VID Output Voltage Programming VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 U VOUT (V) 1.250V 1.275V 1.200V 1.225V 1.150V 1.175V 1.100V 1.125V 1.050V 1.075V 1.800V 1.825V 1.750V 1.775V 1.700V 1.725V 1.650V 1.675V 1.600V 1.625V 1.550V 1.575V 1.500V 1.525V 1.450V 1.475V 1.400V 1.425V 1.350V 1.375V 1.300V 1.325V W UU operation may cause the LTC3720 to exceed its maximum junction temperature rating or RMS current rating. Most of the supply current drives the MOSFET gates unless an external EXTVCC source is used. In continuous mode operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)). The junction temperature can be estimated from the equations given in Note 3 of the Electrical Characteristics. For example, the LTC3720EGN is limited to less than 19mA from a 30V supply: TJ = 70C + (19mA)(30V)(95C/W) = 125C For larger currents, consider using an external supply with the EXTVCC pin. EXTVCC Connection The EXTVCC pin can be used to provide MOSFET gate drive and control power from an external source during normal operation. Whenever the EXTVCC pin is above 4.7V the internal 5V regulator is shut off and an internal 50mA Pchannel switch connects the EXTVCC pin to INTVCC. INTVCC power is supplied from EXTVCC until this pin drops below 4.5V. Do not apply more than 7V to the EXTVCC pin and ensure that EXTVCC VIN. The following list summarizes the possible connections for EXTVCC: 1. EXTVCC grounded. INTVCC is always powered from the internal 5V regulator. 2. EXTVCC connected to an external supply. A high efficiency supply compatible with the MOSFET gate drive requirements (typically 5V) can improve overall efficiency. 3. EXTVCC connected to an output derived boost network. The low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7V. The system will start-up using the internal linear regulator until the boosted output supply is available. 3720f 15 LTC3720 APPLICATIO S I FOR ATIO External Gate Drive Buffers The LTC3720 drivers are adequate for driving up to about 60nC into MOSFET switches with RMS currents of 50mA. Applications with larger MOSFET switches or operating at higher frequencies requiring greater RMS currents will benefit from using external gate drive buffers such as the LTC1693. Alternately, the external buffer circuit shown in Figure 5 can be used. Note that the bipolar devices reduce the signal swing at the MOSFET gate and benefit from an increased EXTVCC voltage of about 6V. BOOST Q1 FMMT619 10 TG Q2 FMMT720 SW GATE OF M1 10 BG Q4 FMMT720 PGND 3720 F05 INTVCC Q3 FMMT619 GATE OF M2 Figure 5. Optional External Gate Driver Soft-Start and Latchoff with the RUN/SS Pin The RUN/SS pin provides a means to shut down the LTC3720 as well as a timer for soft-start and overcurrent latchoff. Pulling the RUN/SS pin below 0.8V puts the LTC3720 into a low quiescent current shutdown (IQ < 30A). Releasing the pin allows an internal 1.2A current source to charge up the external timing capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about: tDELAY = 1.5V C SS = 1.3s/F C SS 1.2A ( ) When the voltage on RUN/SS reaches 1.5V, the LTC3720 begins operating with a clamp on ITH of approximately 0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH is raised until its full 2.4V range is available. This takes an additional 1.3s/F, during which the load current is folded 16 U INTVCC RSS* RUN/SS RSS* D2* RUN/SS VIN 3.3V OR 5V D1 CSS CSS 3720 F06 W UU *OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF (6a) (6b) Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated back until the output reaches 75% of its final value. The pin can be driven from logic as shown in Figure 6. Diode D1 reduces the start delay while allowing CSS to charge up slowly for the soft-start function. After the controller has been started and given adequate time to charge up the output capacitor, CSS is used as a short-circuit timer. After the RUN/SS pin charges above 4V, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. A 1.8A current then begins discharging CSS. If the fault condition persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation. The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has reached the 4V threshold. In general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. A minimum soft-start capacitor can be estimated from: CSS > COUT VOUT RSENSE (10 - 4 [F/V s]) Generally 0.1F is more than sufficient. Overcurrent latchoff operation is not always needed or desired. Load current is already limited during a shortcircuit by the current foldback circuitry and latchoff 3720f LTC3720 APPLICATIO S I FOR ATIO operation can prove annoying during troubleshooting. The feature can be overridden by adding a pull-up current greater than 5A to the RUN/SS pin. The additional current prevents the discharge of CSS during a fault and also shortens the soft-start period. Using a resistor to V IN as shown in Figure 6a is simple, but slightly increases shutdown current. Connecting a resistor to INTVCC as shown in Figure 6b eliminates the additional shutdown current, but requires a diode to isolate CSS. Any pull-up network must be able to pull RUN/SS above the 4.5V maximum threshold that arms the latchoff circuit and overcome the 4A maximum discharge current. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3720 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01 and RL = 0.005, the loss will range from 1% up to 10% as the output current varies from 1A to 10A for a 1.5V output. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: Transition Loss (1.7A-1) VIN2 IOUT CRSS f U 3. INTVCC current. This is the sum of the MOSFET driver and control currents. This loss can be reduced by supplying INTVCC current through the EXTVCC pin from a high efficiency source, such as an output derived boost network or alternate supply if available. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components shown in Figure 7 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Application Note 76. 3720f W UU 17 LTC3720 APPLICATIO S I FOR ATIO Design Example As a design example, take a supply with the following specifications: VIN = 7V to 24V (15V nominal), VOUT = 1.05V to 1.825V with typical at 1.5V, IOUT(MAX) = 15A, f = 300kHz. First, calculate the timing resistor with VON = VOUT: RON = ( 1 300kHz 10pF )( ) = 330k and choose the inductor for about 40% ripple current at the maximum VIN: L= ( 1.5V 1- = 0.8H 300kHz 0.4 15A 24V 1.5V )( )( ) )( ) Selecting a standard value of 1H results in a maximum ripple current of: IL = ( 1.5V 1- = 4.7A 300kHz 1H 24V 1.5V Next, choose the synchronous MOSFET switch. Because of the narrow duty cycle and large current, a single SO-8 MOSFET will have difficulty dissipating the power lost in the switch. Choosing two IRF7811A (RDS(ON) = 0.013, CRSS = 60pF, JA = 50C/W) yields a nominal sense voltage of: VSNS(NOM) = (15A)(0.5)(1.3)(0.012) = 117mV Tying VRNG to INTVCC will set the current sense voltage range for a nominal value of 140mV with current limit occurring at 186mV. To check if the current limit is acceptable, assume a junction temperature of about 100C above a 50C ambient with 150C = 1.6: 18 U ILIMIT W UU (0.5)(1.6)(0.012) ( ) 186mV + 2 1 4.7A = 18A 2 and double check the assumed TJ in the MOSFET: PBOT 24V - 1.5V 21.7 A = 1.6 0.012 = 2.12 W 24V 2 ( )( ) TJ = 50C + (2.12W)(50C/W) = 156C Because the top MOSFET is on for such a short time, a single IRF7811A will be sufficient. Checking its power dissipation at current limit with 90C = 1.3: PBOT = ) (1.3)(0.012) + 2 (1.7)(24V) (21.7A)(60pF )(300kHz) 1.5V 21.7A 24V 2 ( = 0.46W + 0.38W = 0.84 W TJ = 50C + (0.84W)(50C/W) = 92C The junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. CIN is chosen for an RMS current rating of about 6A at temperature. The output capacitors are chosen for a low ESR of 0.005 to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: VOUT(RIPPLE) = IL(MAX) (ESR) = (4.7A) (0.005) = 24mV 3720f LTC3720 APPLICATIO S I FOR ATIO However, a 0A to 15A load step will cause an output change of up to: VOUT(STEP) = ILOAD (ESR) = (15A) (0.005) = 75mV The complete circuit is shown in Figure 7. Active Voltage Positioning Active voltage positioning (also termed load "deregulation" or droop) describes a technique where the output voltage varies with load in a controlled manner. It is useful in applications where rapid load steps are the main cause of error in the output voltage. By positioning the output voltage above the regulation point at zero load, and below the regulation point at full load, one can use more of the INT VCC 100k POWER GOOD 1 CSS 0.1F 2 3 CC2 100pF INT VCC CC1 500pF RC 20k 4 5 6 7 8 CION 0.01F CFB 100pF 330k 9 10 C2 6.8nF VIN 11 12 13 14 28 RUN/SS VON PGOOD VRNG FCB ITH LTC3720 SGND ION VFB SGND VFB VOSENSE VID0 VID1 BG 21 INTVCC 20 VIN 19 EXTVCC 18 VCC 17 VID4 16 VID3 15 VID2 CF 0.1F 4.7F 6.3V 1 BOOST 27 TG 26 SW SENSE+ SENSE- PGND 22 25 24 23 DB CMDSH-3 RF 10 CB 0.33F Figure 7. 15A CPU Core Voltage Regulator at 300kHz U error budget for the load step. This allows one to reduce the number of output capacitors by relaxing the ESR requirement. In the design example, Figure 7, five 0.025 capacitors are required in parallel to keep the output voltage within tolerance. Using active voltage positioning, the same specification can be met with only three capacitors. In this case, the load step will cause an output voltage change of: 1 VOUT (STEP) = 15A 0.025 = 125mV 3 W UU ()( ) VIN 7V TO 24V CIN 10F 50V x3 M1 IRF7811A L1 1H UPS840 VOUT 1.05V TO 1.825V 15A M2 IRF7811A x2 + COUT 270F 2V x5 SGND 3720 F07 3720f 19 LTC3720 APPLICATIO S I FOR ATIO By positioning the output voltage 60mV above the regulation point at no load, it will only drop 65mV below the regulation point after the load step, well within the 100mV tolerance. Implementing active voltage positioning requires setting a precise gain between the sensed current and the output voltage. Because of the variability of MOSFET on-resistance, it is prudent to use a sense resistor with active voltage positioning. In order to minimize power lost in this resistor, a low value is chosen of 0.003. The nominal sense voltage will now be: VSNS(NOM) = (0.003)(15A) = 45mV To maintain a reasonable current limit, the voltage on the VRNG pin is reduced to its minimum value of 0.5V, corresponding to a 50mV nominal sense voltage. Next, the gain of the LTC3720 error amplifier must be determined. The change in ITH voltage for a corresponding change in the output current is: 12V ITH = RSENSE IOUT VRNG = 24 0.003 15A = 1.08V The corresponding change in the output voltage is determined by the gain of the error amplifier and feedback divider. The LTC3720 error amplifier has a transconductance gm that is constant over both temperature and a wide 40mV input range. Thus, by connecting a load resistance RVP to the ITH pin, the error amplifier gain can be precisely set for accurate active voltage positioning. ( )( )( ) 0.8V ITH = gm RVP VOUT VOUT 20 U Solving for this resistance value: RVP = = VOUT ITH (0.8V)gm VOUT (1.5V)(1.08V) = 9.53k (0.8V)(1.7mS)(125mV) W UU The gain setting resistance RVP is implemented with two resistors, RVP1 connected from ITH to ground and RVP2 connected from ITH to INTVCC. The parallel combination of these resistors must equal RVP and their ratio determines nominal value of the ITH pin voltage when the error amplifier input is zero. To center the load line around the regulation point, the ITH pin voltage must be set to correspond to half the output current. The relation between ITH voltage and the output current is: 12V 1 ITH(NOM) = RSENSE IOUT - IL + 0.8V 2 VRNG 12V 1 = 0.003 7.5A - 4.7A + 0.8V 2 0.5V = 1.17V ( ) Solving for the required values of the resistors: RVP1 = 5V 5V 9.53k RVP = 5V - ITH(NOM) 5V - 1.17V = 12.44k 5V 5V 9.53k = 40.73k RVP2 = RVP = 1.17V ITH(NOM) 3720f LTC3720 APPLICATIO S I FOR ATIO The modified circuit is shown in Figure 8. Figures 9 and 10 show the transient response without and with active voltage positioning. Both circuits easily stay within 100mV of the 1.5V output. However, the circuit with active voltage INT VCC 100k CSS 0.1pF POWER GOOD 1 2 RRNG1 4.99k INT VCC RVP2 40.2k RVP1 12.4k CC 180pF RRNG2 45.3k 3 4 5 6 7 8 CION 0.01F 9 330k 10 VIN 11 CFB 100pF 12 13 14 28 RUN/SS VON PGOOD VRNG FCB ITH LTC3720 SGND ION VFB SGND VFB VOSENSE VID0 VID1 BG 21 INTVCC 20 VIN 19 EXTVCC 18 VCC 17 VID4 16 VID3 15 VID2 BOOST 27 TG 26 SW SENSE+ SENSE- PGND 22 25 24 23 Figure 8. 15A CPU Core Voltage Regulator with Active Voltage Positioning at 300kHz VOUT 100mV/DIV 1.5V IL 10A/DIV COUT = 5 x 270F VIN = 15V FIGURE 7 CIRCUIT 20s/DIV 3720 F09 Figure 9. Normal Transient Response (COUT = 5 x 270F) U positioning accomplishes this with only three output capacitors rather than five. Refer to Linear Technology Design Solutions 10 for additional information about active voltage positioning. VIN 5V TO 24V RF 1 CB 0.33F CIN 10F 35V x3 M1 IRF7811A L1 1H DB CMDSH-3 M2 IRF7811A x2 VOUT 1.05V TO 1.825V 15A W UU + + 4.7F 6.3V RSENSE 0.003 UPS840 COUT 270F 2V x3 SGND CF 0.1F 3720 F08 VOUT 100mV/DIV 1.5V IL 10A/DIV COUT = 3 x 270F VIN = 15V FIGURE 8 CIRCUIT 20s/DIV 3720 F10 Figure 10. Transient Response with Active Voltage Positioning (COUT = 3 x 270F) 3720f 21 LTC3720 APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, use the following checklist to ensure proper operation of the controller. These items are also illustrated in Figure 11. * Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. * Place M2 as close to the controller as possible, keeping the SENSE-, BG and SENSE + traces short. * Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. Minimize the loop area formed by CIN, M1 and M2. INT VCC POWER GOOD 1 CSS 2 3 4 CC2 INT VCC CC1 RC CION 5 6 7 8 9 10 VIN 11 12 13 14 28 RUN/SS VON PGOOD VRNG FCB ITH LTC3720 SGND ION VFB SGND VFB VOSENSE VID0 VID1 BG 21 INTVCC 20 VIN 19 EXTVCC 18 VCC 17 VID4 16 VID3 15 VID2 CF BOOST 27 TG 26 SW SENSE+ SENSE- PGND 22 25 24 23 RON BOLD LINES INDICATE HIGH CURRENT PATHS Figure 11. LTC3720 Layout Diagram 22 U * Keep the high dV/dT SW, BOOST and TG nodes away from sensitive small-signal nodes. * Connect the INTVCC decoupling capacitor CVCC closely to the INTVCC and PGND pins. * Connect the top driver boost capacitor CB closely to the BOOST and SW pins. * Connect the VIN pin decoupling capacitor CF closely to the VIN and PGND pins. * VID0-VID4 interface circuitry must return to SGND. VIN RF 10 CB M1 CIN L1 1H VOUT DB M2 D1 W UU + COUT + SGND 3720 F11 3720f LTC3720 PACKAGE DESCRIPTIO .254 MIN .0165 .0015 RECOMMENDED SOLDER PAD LAYOUT .0075 - .0098 (0.191 - 0.249) .016 - .050 (0.406 - 1.270) 0 - 8 TYP NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 .005 .386 - .393* (9.804 - 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615 .033 (0.838) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 TYP 1 .053 - .069 (1.351 - 1.748) 23 4 56 7 8 9 10 11 12 13 14 .004 - .009 (0.102 - 0.249) .015 .004 x 45 (0.38 0.10) .008 - .012 (0.203 - 0.305) .0250 (0.635) BSC GN28 (SSOP) 0502 3720f 23 LTC3720 RELATED PARTS PART NUMBER LTC1628-PG LTC1628-SYNC DESCRIPTION Dual, 2-Phase Synchronous Step-Down Controller Dual, 2-Phase Synchronous Step-Down Controller COMMENTS Power Good Output, Minimum Input/Output Capacitors, 3.5V VIN 36V Synchronizable 150kHz to 300kHz Up to 42A Outputs, Various VID Tables, Mobile, Desktop, Server, 3.5V VIN 36V Burst ModeTM Operation, 16-Pin Narrow SSOP, 3.5V VIN 36V Mobile VID, 0.925V VOUT 2V, 3.5V VIN 36V Current Mode, 550kHz, Very Small Solution Size Up to 95% Efficiency, 550kHz, 2.65V VIN 8.5V, 0.8V VOUT VIN, Synchronizable to 750kHz No Sense Resistor Required, 4V VIN 36V, 0.8V VOUT (0.9) VIN 2.6V VIN 36V, Power Good Output, 300kHz Operation Current Mode,550kHz, Small 16-Pin SSOP, 2.5V VIN < 9.8V 0.925V VOUT 2V, VIN up to 36V, 24-Pin GN Phase Lockable Fixed Frequency from 250kHz to 550kHz, 5mm x 5mm QFN and SSOP Packages, Small Inductors and Capacitors, Integrated MOSFET Drivers IMVP III and VRM 9.0/9.1 Compliant, 600kHz per Phase, IOUT 60A, Integrated MOSFET Drivers VOUT = 1/2 VIN, IOUT up to 15A, 3V VIN 8V, 700A Supply Current, 16-Pin SSOP Package LTC1709-7/-8/-8.5/-9 2-Phase Synchronous Step-Down Controllers with 5-Bit VID LTC1735 LTC1736 LTC1772 LTC1773 Synchronous Step-Down Controller Synchronous Step-Down Controller with 5-Bit VID SOT-23 Step-Down Controller Synchronous Step-Down Controller LTC1778/LTC1778-1 No RSENSE Synchronous Step-Down Controllers LTC3778 LTC1876 LTC3701 LTC3711 LTC3728LX LTC3728/LTC3728L LTC3730/LTC3732 LTC3831 2-Phase, Dual Synchronous Step-Down Controller with Step-Up Regulator Dual, 2-Phase Step-Down Controller 5-Bit Adjustible, Low Duty Cycle Step-Down Controller Dual, 550kHz, 2-Phase Synchronous Step-Down Controllers 3-Phase Synchronous DC/DC Step-Down Controllers DDR Memory Termination Power Supply Burst Mode is registered trademark of Linear Technology Corporation. 3720f 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q LT/TP 0203 2K * PRINTED IN USA www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2002 |
Price & Availability of LTC3720EGN
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |